overclockzonefanpage  overclockzoneth  TV  
Page 1 of 2 12 LastLast
Results 1 to 20 of 38
  1. #1
    OverclockZone Member 111111's Avatar
    Join Date
    14 Nov 2007
    Location
    Hiroshima, Japan.

    Default :: The History OF AMD :: จนกว่าจะถึงวันนี้ AMD ( Warning ! Heavy Image )



    AMD Is Born

    From its conception in 1969, AMD focused on producing microprocessors and similar computer components. Initially, it merely licensed processor designs from other companies like Fairchild Semiconductor. Although it started producing other PC components developed entirely in-house early on as well, AMD wouldn't produce a processor it designed itself for several years.



    AM9080 And AM2900

    In 1975, AMD created its first two non-licensed processor products. Technically, its AM2900 wasn't a processor; rather, it was a series of components used to build a 4-bit modular processor. It also produced the AM9080, which was a reverse-engineered clone of Intel's 8080 8-bit microprocessor.



    The IBM Agreement

    AMD's entry into the x86 processor market began in the early 1980s following an agreement between IBM and Intel. At the time, IBM was one of the largest computer manufacturers in the world and quite possibly the single largest producer of computer products. IBM was deliberating on several different processor designs to use in its upcoming products when it entered into negotiations with Intel. If Intel won the contract, it would secure a massive order for the company's processors for use inside of IBM-compatible PCs.
    IBM was concerned, however, that the sheer number of processors that it needed would exceed the production capabilities of any single manufacturer, so it required Intel to license its technology to third-party manufacturers to ensure sufficient total volume. Intel, not wanting to lose the contract with IBM to a competitor, agreed to IBM's terms in 1981.
    Following the agreement, AMD began producing licensed identical clones of Intel's 8086 processors in 1982.

    Code Name N/A
    Release Date 1982
    Architecture 16-bit
    Data Bus 16-bit
    Address Bus 20-bit
    Maximum Memory Support 1 MB
    L1 Cache None
    L2 Cache None
    Frequency 4 - 10 MHz
    FSB 4 - 10 MHz
    FPU 8087 (Sold Separate)
    SIMD None
    Fab 3000 nm
    Transistor Count 29,000
    Power Consumption N/A
    Voltage 5 V
    Die Area 33 mm?
    Socket 40 pins



    AM29000 32-Bit RISC Processors

    Throughout the 1980s and into the 1990s, AMD also produced a line of 32-bit RISC processors known as the AM29000 series. These processors were essentially the next generation of its earlier AM2900 products, however, and they were targeted more at the embedded market than high-performance computers. AMD designed the AM29000 using a variation of the Berkeley RISC architecture. Eventually, AMD discontinued work on the AM29000 series to focus on its x86 processor line.



    AMD's second x86 processor was the AM286, a licensed clone of Intel's 80286. Although the chip was architecturally identical, it had one advantage over its Intel counterpart: higher clock speeds. Where Intel capped the 80286 at 12.5 MHz, AMD pushed the AM286 as high as 20 MHz.
    AMD AM286

    Code Name N/A
    Release Date 1983
    Architecture 16-bit
    Data Bus 16-bit
    Address Bus 24-bit
    Maximum Memory Support 16 MB



    AMD AM386: Legal Battles With Intel

    In 1985, Intel released its first 32-bit x86 processor design, the 80386. AMD planned to release its variation, the AM386, not long after, but Intel held it up in court. Intel claimed that its cross-licensing agreement permitted AMD to produce copies of only the 80286 and older processor designs, but AMD argued that the contract permitted it to create clones of the 80386 and future x86 derivatives, as well. After years of legal battles, the courts sided with AMD, and the company was able to release its AM386 in 1991.
    Although the AM386 is an 80386 clone, AMD released AM386 processors with clock speeds up to 40 MHz, whereas Intel's 80386 tapped out at 33 MHz. This gave AMD a performance advantage, and as it used the same socket and platform as the 80386, it gave customers an upgrade path to their aging systems.
    AMD AM386

    Code Name N/A
    Date 1991
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache None
    L2 Cache None
    Frequency 12 - 40 MHz
    FSB 12 - 40 MHz
    FPU 80387
    SIMD None
    Fab 1500 - 1000 nm
    Transistor Count 275,000
    Power Consumption 2 W (@33 MHz)
    Voltage 5 V
    Die Area 42 mm?
    Socket 132 pins



    AM486 And AMD 5x86: The Final Clone

    The last processor designed by Intel that AMD produced was the AM486 (80486), and it was released in 1994. Due to ongoing legal disputes between Intel and AMD, some versions of the AM486 use Intel microcode whereas others use microcode developed in-house by AMD. AMD followed a similar strategy with its AM486 as it did with the AM386, by pushing clock speed considerably higher than Intel. Although Intel's fastest 80486 processors were capped at 100 MHz, AMD went as high as 120 MHz on the AM486.
    Not long after, in 1995, AMD also released its AMD 5x86. This processor used the same architecture as the AM486 and 80486, but it pushed the clock speed even higher. Retail models ran at 133 MHz, and OEMs had access to an even faster 150 MHz version.
    Other notable changes in this line of processors was the addition of L1 cache, which helped to increase performance compared to the older 80386/AM386 CPUs. It also moved the FPU into the same package as the CPU, which also significantly improved performance. Prior to this, all FPUs were sold as separate hardware units and connected to the CPU through the motherboard.
    Following the release of Intel's first Pentium processor around the same time also lead AMD and other competing CPU designers to introduce the PR or "Pentium Rating" system. This gave companies a simple way to advertise their products against each other and against Intel's Pentium. An example of this is the AMD 5x86 PR 75, which was advertised as having equivalent performance to a 75 MHz Pentium CPU.
    AM486 And AMD 5x86

    Code Name N/A X5
    Date 1993 1995
    Architecture 32-bit 32-bit
    Data Bus 32-bit 32-bit
    Address Bus 32-bit 32-bit
    Maximum Memory Support 4 GB 4 GB
    L1 Cache 8 - 16 KB 16 KB
    L2 Cache None None
    Clock Speed 16 - 120 MHz 133 -150 MHz
    FSB 16 - 50 MHz 33 - 50 MHz
    FPU Integrated Integrated
    SIMD None None
    Fab 800 - 1000 nm 350 nm
    Transistor Count 1,185,000 N/A
    Power Consumption N/A N/A
    Voltage 5 V - 3.3 V 3.45 V
    Die Area 67 - 81 mm? N/A
    Socket 168 pins 168 pins



    K5: AMD's First x86 Processor

    In 1996, AMD released its first x86 processor designed entirely in-house. The fifth-generation x86 K5 processor used an innovative design that combined the execution hardware from AMD's discontinued AM29000 RISC processors with an x86 front end. Because the execution back-end hardware was based on a RISC design, instructions were decoded into micro-instructions that could be fed into one of five integer execution units or an integrated FPU.
    AMD implemented an out-of-order speculative execution design as well, which helped to boost performance. The overall design was fairly complex, however, which limited AMD's ability to push up the clock speed, and the K5 was not able to surpass Intel's Pentium in terms of performance. It was considered relatively efficient, however, and AMD advertised 100 MHz K5 processors with a PR133 rating, meaning that AMD considered it to have equivalent performance to a 133 MHz Pentium.
    AMD K5

    Code Name SSA/5, 5k86
    Date 1996
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 16 KB + 8 KB
    L2 Cache None
    Clock Speed 75 - 133 MHz (PR75 - PR200)
    FSB 50 - 66 MHz
    SIMD None
    Fab 500 - 350 nm
    Transistor Count 4.3 Million
    Power Consumption 11 - 16 W
    Voltage 3.52 V
    Die Area 181 - 251 mm?
    Connection Socket 5 & Socket 7



    K6: AMD's NexGen Processor

    Instead of developing a new architecture to succeed the K5, AMD opted to purchase NexGen, a competing manufacturer of processors, and use its upcoming Nx686 design for the K6. Although the design was completely different than the K5, it was somewhat similar at a high level.
    For example, like the K5, the K6 also used an x86 front-end to decode instructions into micro-operations that were then executed on internally RISC-like hardware. The K6 was released in 1997, and it was compatible with Socket 7 motherboards; clock-for-clock, it matched the performance of Intel's Pentium II, while also being considerably less expensive. It also included the important MMX SIMD instruction set.
    The Pentium II did have one major advantage in that its FPU performance was better than the K6.
    AMD K6

    Code Name K6 (350 nm), Little Foot (250 nm)
    Date 1997/1998
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 32 KB + 32 KB
    L2 Cache None
    L3 Cache None
    Clock Speed 266 - 350 MHz
    FSB 50 - 66 MHz
    SIMD MMX
    Fab 350 - 250 nm
    Transistor Count 8.8 Million
    Power Consumption 12 - 28 W
    Voltage 2,2 - 3,2 V
    Die Area 68 - 157 mm?
    Socket Socket 7



    AMD K6-II

    AMD's next processor was the K6-II. It was essentially an extended version of the K6 that could use a faster 100 MHz FSB, higher clock speeds, and new SIMD instructions. AMD introduced its 3DNow! SIMD instruction set as a competitor to Intel's MMX. Similar to AMD's older processors, the K6-II gave customers a clear upgrade path from the aging Pentium MMX processors, and as a result they were highly successful.
    AMD K6-II

    Code Name K6-3D, Chomper
    Date 1998
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 32 KB + 32 KB
    L2 Cache None
    L3 Cache None
    Clock Speed 300 - 550 MHz
    FSB 66 - 100 MHz
    SIMD MMX, 3DNow!
    Fab 250 nm
    Transistor Count 9.3 Million
    Power Consumption 13 - 25 W
    Voltage 2.2 - 2.4 V
    Die Area 81 mm?
    Socket Socket 7/Super Socket 7



    AMD K6-III: Integration Of L2 Cache

    In 1999, AMD released its third-generation K6 processor, the K6-III. It was architecturally similar to the K6 and K6-II, but AMD added 256 KB of L2 cache on the CPU die. Prior to this, L2 was placed on the motherboard and accessed over the FSB, but the tighter integration significantly reduced latency and increased bandwidth. The K6-III was relatively expensive, however, and AMD quickly replaced it with the Athlon processor.
    AMD K6-III

    Code Name Sharptooth
    Date 1999
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 32 KB + 32 KB
    L2 Cache 256 KB (350 - 550 MHz)
    L3 Cache None
    Clock Speed 350 - 550 MHz
    FSB 100 MHz
    SIMD MMX, 3DNow!
    Fab 250 nm
    Transistor Count 21.3 Million
    Power Consumption 10 - 17 W
    Voltage 2.2 - 2.4 V
    Die Area 118 mm?
    Socket Super Socket 7



    AMD K6-II+ And K6-III+

    The last processors released by AMD in the K6 product line were the K6-II+ and K6-III+, which were targeted at the mobile market. These processors were similar to the K6-III in that they incorporated on-die L2 cache. The K6-II+ had 128 KB of L2, whereas the K6-III+ had 256 KB. Thanks to the use of AMD's 180 nm fab technology, these processors were relatively energy efficient.
    AMD K6-II+ And K6-III+

    Code Name N/A
    Date 2000
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 32 KB + 32 KB
    L2 Cache 128 - 256 KB (400 - 550 MHz)
    L3 Cache None
    Clock Speed 400 - 550 MHz
    FSB 100 MHz
    SIMD MMX, 3DNow!
    Fab 180 nm
    Transistor Count N/A
    Power Consumption N/A
    Voltage 1.6 - 2.0 V
    Die Area N/A
    Socket N/A



    AMD K7 And K75: The Birth Of Athlon

    In 1999, AMD released its seventh-generation processor, the Athlon. It used a new architecture that increased IPC considerably and allowed AMD to push the clock rates up to 1 GHz. The FPU inside of AMD's previous processors had lagged behind competing Intel products, so improving the FPU was one of the primary objectives of the design team. This lead to the Athlon being equipped with an exceedingly powerful triple-issue out-of-order FPU that surpassed Intel's competing processors.
    The first processor models placed the CPU core on a large silicon card. Instead of using on-die L2 cache, AMD used separate RAM chips soldered onto the same package as the CPU. This enabled AMD to install larger amounts of L2, but the cache ran at lower clock speeds.
    Licensing DEC's EV6 FSB technology allowed AMD to design its own chipsets, leading to the first all-AMD platforms. Unfortunately, those first motherboards fell short of what Intel's competing 440BX could do. The EV6 FSB also made the Athlon compatible with new DDR RAM, which featured greater bandwidth and performance compared to traditional SDRAM.
    AMD K7 And K75

    Code Name Argon (K7) Pluto, Orion (K75)
    Date June 1999 November 1999
    Architecture 32-bit 32-bit
    Data Bus 32-bit 32-bit
    Address Bus 32-bit 32-bit
    Maximum Memory Support 4 GB 4 GB
    L1 Cache 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache 512 KB (1/2 CPU) 512 KB (1/2, 2/5, 1/3 CPU)
    Clock Speed 500 - 700 MHz 550 - 850 MHz (Pluto)
    900 - 1000 MHz (Orion)
    FSB 100 MHz (DDR) 100 MHz (DDR)
    SIMD MMX, Enhanced 3DNow! MMX, Enhanced 3DNow!
    Fab 250 nm 180 nm
    Transistor Count 22 Million 22 Million
    Power Consumption 42 - 50 W 31 - 65 W
    Voltage 1.6 V 1.6 - 1.8 V
    Die Area 184 mm? 102 mm?
    Socket Slot A Slot A



    AMD K7: Athlon Thunderbird

    Not long after the release of AMD's Athlon on Slot A and Intel's Pentium II and III for Slot 1, the industry realized that the lackluster performance of the L2 cache was hampering CPU performance. To overcome this issue, AMD reverted back to a traditional processor package with its Athlon Thunderbird, which contained L2 cache integrated directly onto the CPU die. Although the L2 cache size was cut in half, it ran at the same speed as the CPU, drastically improving performance.
    Thanks to a maturing 180 nm process and higher yields, AMD also took this opportunity to boost the clock speed of its CPUs by 400 MHz.
    AMD Athlon Thunderbird

    Code Name Thunderbird
    Date 2000
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 64 KB + 64 KB
    L2 Cache 256 KB (Full Speed)
    Frequency 600 - 1400 MHz
    FSB 100, 133 MHz (DDR)
    SIMD MMX, Enhanced 3DNow!
    Fab 180 nm
    Transistor Count 37 Million
    Power Consumption 38 - 72 W
    Voltage 1.7 - 1.75 V
    Die Area 120 mm?
    Socket Socket A



    K7: AMD Duron

    o target the entry-level segment and to make use of its lower yield chips, AMD introduced the Duron product line. These processors used the same architecture but generally ran at lower clock speeds. AMD also disabled all but 64 KB of the L2 cache on these processors, which reduced performance, but the Duron still was quite competitive against Intel's Celeron products.
    AMD Duron

    Code Name Spitfire/Morgan
    Date 2000/2001
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 64 KB + 64 KB
    L2 Cache 64 KB (Full Speed)
    Frequency 600 - 950 MHz (Spitfire) 900 - 1300 MHz (Morgan)
    FSB 100 (DDR)
    SIMD MMX, Enhanced 3DNow!
    Fab 180 nm
    Transistor Count 37 Million
    Power Consumption N/A
    Voltage 1.5 - 1.75 V
    Die Area 120 mm?
    Socket Socket A



    AMD K7: Athlon Palomino/XP

    In 2001, AMD improved the Athlon again with the Palomino/XP. Little changed between the Thunderbird and the Palomino/XP, but the ever-maturing 180 nm process enabled AMD to push clock speeds up another 333 MHz. It also added support for the SSE SIMD instruction set. Microsoft's Windows XP launched around the same time, so AMD added "XP" to the Palomino code name to help advertise it towards users of the new operating system.
    Versions of the Athlon Palomino/XP were also sold under the name "Athlon MP" for servers and "Athlon 4" or "Athlon XP Mobile" for laptop computers.
    AMD Athlon Palomino/XP

    Code Name Palomino/XP
    Date May 2001
    Architecture 32-bit
    Data Bus 32-bit
    Address Bus 32-bit
    Maximum Memory Support 4 GB
    L1 Cache 64 KB + 64 KB
    L2 Cache 256 KB (Full Speed)
    Frequency 850 - 1733 MHz
    FSB 133 MHz (DDR)
    SIMD MMX, Enhanced 3DNow!, SSE
    Fab 180 nm
    Transistor Count 37.5 Million
    Power Consumption 46 - 72 W
    Voltage 1.75 V
    Die Area 129.26 mm?
    Socket Socket A



    AMD K7: Athlon Thoroughbred And Barton

    In 2002, AMD rolled out the Athlon Thoroughbred, which was produced on a new 130nm process. This helped lower power consumption push frequencies over 2 GHz. As the process matured, AMD introduced the Barton a year later. Barton brought a modest clock rate increase, and it also doubled the size of the L2 cache and added support for 200 MHz FSB and 400 MHz DDR RAM.
    AMD Athlon Thoroughbred and Barton

    Code Name Thoroughbred Barton
    Date April 2002 February 2003
    Architecture 32-bit 32-bit
    Data Bus 32-bit 32-bit
    Address Bus 32-bit 32-bit
    Maximum Memory Support 4 GB 4 GB
    L1 Cache 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache 256 KB (Full Speed) 512 KB (Full Speed)
    Frequency 1 - 2.25 GHz 1.3 - 2.33 GHz
    FSB 100 - 166 MHz (DDR) 100 - 200 MHz (DDR)
    SIMD MMX, Enhanced 3DNow!, SSE MMX, Enhanced 3DNow!, SSE
    Fab 130 nm 130 nm
    Transistor Count 37.2 Million 54.3 Million
    Power Consumption 49 - 68 W 60 - 76 W
    Voltage 1.5 -1.65 V 1.65 V
    Die Area 84.66 mm? 100.99 mm?
    Socket Socket A Socket A



    AMD K7: Athlon Thorton And Duron

    Alongside Barton, AMD released two lower-end processors, the Athlon Thorton and a new Duron. Both processors used the same die as Barton but with part of the L2 cache disabled.
    Thorton had 256 KB of L2 cache. similar to older Athlon processors, and it ran at slightly lower clock speeds than Barton. Thanks to the new 130nm fab technology, it was also more energy efficient than the older Athlon CPUs. The new Duron chip was limited to 64 KB of L2 cache, just like the previous Duron processors, but it was available at clock speeds up to 1.8 GHz, making the high-end models considerably faster than their predecessors.
    AMD Athlon Thorton and Duron

    Code Name Thorton Duron
    Date 2003 2003
    Architecture 32-bit 32-bit
    Data Bus 32-bit 32-bit
    Address Bus 32-bit 32-bit
    Maximum Memory Support 4 GB 4 GB
    L1 Cache 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache 256 KB (Full Speed) 64 KB (Full Speed)
    Frequency 1.6 - 2.2 GHz 1.4 - 1.8 GHz
    FSB 100 - 200 MHz (DDR) 133 MHz (DDR)
    SIMD MMX, Enhanced 3DNow!, SSE MMX, Enhanced 3DNow!, SSE
    Fab 130 nm 130 nm
    Transistor Count 54.3 Million 54.3 Million
    Power Consumption N/A N/A
    Voltage 1.5 -1.65 V 1.5 V
    Die Area 100.99 mm? 100.99 mm?
    Socket Socket A Socket A



    AMD Geode: The APU Predecessor

    AMD purchased the Geode processor line in 2003 from National Semiconductor to extend its low-end product offerings. The Geodes actually had roots in another company called Cyrix, which created the MediaGX product line in the late 1990s as a single-chip solution containing a general-purpose processor, sound chip, graphics accelerator and all of the hardware typically inside of a motherboard's chipset. When Cyrix went out of business, National Semiconductor picked up the MediaGX and transformed it into the Geode.
    AMD launched two processors under the "Geode" name. At the extreme low-end was the Geode GX series, which was identical to the products sold by National Semiconductor. As a somewhat higher-performance solution, AMD also introduced the LX series, which contained several enhancements including the transition to AMD's K7 Athlon architecture for the CPU. These products were highly efficient and were used in several inexpensive and thin-client devices.
    AMD Geode

    Code Name GX-Series LX-Series
    Date 2003 2003
    Architecture 32-bit 32-bit
    Data Bus 32-bit 32-bit
    Address Bus 32-bit 32-bit
    Maximum Memory Support 4 GB 4 GB
    L1 Cache 16 KB 64 KB + 64 KB
    L2 Cache N/A 128 KB (Full Speed)
    Frequency 333 - 400 MHz 366 - 600 MHz
    FSB N/A 166 - 200 MHz (DDR)
    SIMD N/A N/A
    Fab N/A 130 nm
    Transistor Count N/A N/A
    Power Consumption N/A N/A
    Voltage N/A N/A
    Die Area N/A N/A
    Socket N/A N/A


    AMD K7: First Sempron

    AMD released its first Sempron-branded products in 2004. Initially, they slid in between the high-end Athlon Barton processors and the low-end Duron, filling roughly the same space as the Athlon Thorton. The first few models used either Thorton or Thoroughbred cores with the full 256 KB of L2 cache. These chips were capped at slightly lower clock speeds, with the fastest SKUs clocked at 2 GHz.
    Just a few months after Sempron was introduced, AMD released a new version based on the Barton core with the full 512 KB of L2 cache and a higher 2.2 GHz clock speed.
    AMD Sempron

    Code Name Thoroughbred/Thorton Barton
    Date July 2004 September 2004
    Architecture 32-bit 32-bit
    Data Bus 32-bit 32-bit
    Address Bus 32-bit 32-bit
    Maximum Memory Support 4 GB 4 GB
    L1 Cache 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache 256 KB (Full Speed) 512 KB (Full Speed)
    Frequency 1.5 - 2.0 GHz 2 - 2.2 GHz
    FSB 166 MHz (DDR) 166 - 200 MHz (DDR)
    SIMD MMX, Enhanced 3DNow!, SSE MMX, Enhanced 3DNow!, SSE
    Fab 130 nm 130 nm
    Transistor Count 37.2 - 54.3 Million 54.3 Million
    Power Consumption N/A N/A
    Voltage 1.6 V 1.6 - 1.65 V
    Die Area 84.66 - 100.99 mm? 100.99 mm?
    Socket Socket A Socket A



    AMD K8: Athlon 64!

    In 2003, AMD shocked the world by introducing the first consumer-oriented 64-bit x86 processor. Codenamed "K8," these processors were essentially heavily modified variations of the K7. By moving to a 64-bit design, AMD was able to extend the memory support to a theoretical 1 TB.
    Although that was more RAM than any K8 system would ever use, PCs were no longer limited to 4 GB of memory, and systems with 8 GB of RAM began showing up on the market. AMD also moved the memory controller from its chipset and integrated it into the CPU die. This drastically reduced memory latency and pushed performance up considerably over the K7. With the memory controller inside of the CPU die, this effectively removed the FSB from the system. Instead, AMD introduced its HyperTransport technology, which was capable of significantly greater bandwidth than the older FSB connection.
    AMD sold the initial batch of K8 chips under the brand names "Athlon 64" for consumers (Clawhammer and Newcastle), "Athlon 64 FX" (Sledgehammer and Clawhammer) for enthusiasts and "Opteron" for servers (Sledgehammer).
    AMD Athlon 64 Sledgehammer, Clawhammer and Newcastle

    Code Name Sledgehammer Newcastle/Clawhammer
    Date 2003/2004 2004
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache 1 MB (Full Speed) 512 KB (Full Speed - Newcastle), 1 MB (Full Speed - Clawhammer)
    Clock Speed 1.4 - 2.4 GHz 1.8 - 2.4 GHz (Newcastle)/ 2 - 2.6 GHz (Clawhammer)
    Memory Controller Single-Channel 400 MHz DDR Single-Channel 400 MHz DDR (Socket 754)/ Dual-Channel 400 MHz DDR (Socket 939)
    HyperTransport 800 MHz 800-1000 MHz
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2 MMX, Enhanced 3DNow!, SSE, SSE2
    Fab 130 nm 130 nm
    Transistor Count 105.9 Million 105.9 Million
    Power Consumption 89 W TDP 89 W TDP
    Voltage 1.5 - 1.55 V 1.5 V
    Die Area 193 mm? 193 mm?
    Socket Socket 940 Socket 754, Socket 939

  2. #2
    OverclockZone Member 111111's Avatar
    Join Date
    14 Nov 2007
    Location
    Hiroshima, Japan.

    Default



    AMD K8: Gradual Improvement

    In 2004, AMD introduced its new 90nm transistor process, which enabled the company to increase the performance of its Athlon 64 processors while also reducing power consumption. AMD produced a total of four 90nm Athlon 64 chips to cover the desktop market.
    Venice became the last Athlon 64 processor released for AMD's Socket 754, and it also was the highest-performing chip available on that platform. AMD's San Diego ran at similar clock speeds, but was targeted at the Socket 939 platform and had a larger 1 MB L2 cache.
    To target more efficient systems, AMD introduced the Winchester core around the same time, which had a lower TDP of 67 W. It was the most energy efficient Athlon 64 processor for several years until the release of the 62 W TDP Orleans in 2006 and the 65nm 45 W Lima in 2007.
    AMD Athlon 64 Winchester, Venice, San Diego, Orleans and Lima

    Code Name Winchester/Venice/San Diego Orleans/Lima
    Date 2004 (Winchester)/2005 (Venice and San Diego) 2006
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache 512 KB (Full Speed - Winchester and Venice)/ 1 MB (Full Speed - San Diego) 512 KB (Full Speed - Orleans and Lima), 1 MB (Full Speed - Lima)
    Clock Speed 1.8 - 2.2 GHz (Winchester)/ 1.8 - 2.4 GHz (Venice)/ 2.2 - 2.6 GHz (San Diego) 1.8 - 2.6 GHz (Orleans)/ 2 - 2.8 GHz (Lima)
    Memory Controller Single-Channel 400 MHz DDR (Venice)/ Dual-Channel 400 MHz DDR (Winchester and San Diego) Dual-Channel DDR2
    HyperTransport 800 MHz (Venice)/ 1000 MHz (Winchester and San Diego) 800-1000 MHz
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3 MMX, Enhanced 3DNow!, SSE, SSE2, SSE3
    Fab 90 nm 90 nm (Orleans)/ 65 nm (Lima)
    Transistor Count N/A N/A
    Power Consumption 64 W TDP (Winchester)/ 89 W TDP (Venice and San Diego) 62 W (Orleans)/ 45 W (Lima)
    Voltage 1.35 - 1.4 V 1.25 - 1.4 V
    Die Area N/A N/A
    Socket Socket 754 (Venice)/ Socket 939 (Winchester and San Diego) Socket AM2



    AMD K8: Sempron

    Alongside the K8 Athlon processors, AMD also updated its Sempron product line with the new K8 architecture. Just like the first Sempron products, these CPUs typically had less cache and lower clock speeds than their Athlon counterparts.
    AMD K8 Sempron

    Code Name Paris, Palermo, Manila, Sparta
    Date 2004 - 2007
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache 64 KB + 64 KB
    L2 Cache 128 - 512 KB (Full Speed)
    Clock Speed 1.4 - 2.3 GHz
    Memory Controller Single-Channel DDR / Dual-Channel DDR / Dual-Channel DDR2
    HyperTransport 800 MHz / 1000 MHz
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3
    Fab 130 - 65 nm
    Transistor Count N/A
    Power Consumption N/A
    Voltage 1.2 - 1.4 V
    Die Area N/A
    Socket Socket 754 / Socket 939 / Socket AM2



    AMD K8: Athlon 64 X2

    Just as it did two years prior, AMD pulled another shocker in 2005 with the introduction of a consumer-oriented dual-core processor based on the K8 architecture. Although the two processors were incapable of working on the same thread simultaneously, the second CPU core could handle other tasks and increase multitasking performance.
    AMD produced a total of six CPU configurations in the Athlon 64 X2 product line, but the first five are all relatively similar to each other, varying only in L2 cache size and clock rate. The sixth Athlon 64 X2 design was the fastest in the series and the most energy efficient, owing to the move to 65nm transistor technology.
    AMD Athlon 64 X2

    Code Name Manchester - Windsor Brisbane
    Date 2005-2006 2006
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache 64 KB + 64 KB Per Core 64 KB + 64 KB Per Core
    L2 Cache 256 KB - 1 MB Per Core (Full Speed) 512 KB Per Core (Full Speed)
    Clock Speed 2 - 3.2 GHz 1.9 - 3.1 GHz
    Memory Controller Dual-Channel DDR/DDR2 Dual-Channel DDR2
    HyperTransport 1000 MHz 1000 MHz
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3 MMX, Enhanced 3DNow!, SSE, SSE2, SSE3
    Fab 90 nm 65 nm
    Transistor Count N/A N/A
    Power Consumption 35 - 125 W TDP 65 - 89 W TDP
    Voltage 1.25 - 1.4 V 1.25 - 1.35 V
    Die Area N/A 126 mm?
    Socket Socket 939, Socket AM2 Socket AM2



    AMD K8: Turion And Turion X2

    AMD introduced a new mobile product line called "Turion" in 2005. These processors used the same architecture as AMD's desktop product, but thanks to careful core binning, they were able to operate with less power. AMD introduced dual-core variants as well, dubbed "Turion X2."
    AMD K8 Turion and Turion X2

    Code Name Turion (Lancaster, Richmond, Sable) Turion X2
    Date 2005 - 2008 2006 - 2008
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache 512 KB - 1 MB (Full Speed) 256 KB - 1 MB Per Core (Full Speed)
    Clock Speed 1.6 - 2.4 GHz 1.6 - 2.5 GHz
    Memory Controller Single-Channel DDR / Dual-Channel DDR2 Dual-Channel DDR2
    HyperTransport 800 MHz / 1000 MHz 800-1000 MHz
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3 MMX, Enhanced 3DNow!, SSE, SSE2, SSE3
    Fab 65 - 90 nm 65 - 90 nm
    Transistor Count N/A N/A
    Power Consumption 25 - 35 W 31 - 35 W
    Voltage 0.8 - 1.35 V N/A
    Die Area N/A N/A
    Socket Socket 754 / Socket S1 Socket S1



    AMD K10: Quad-Core Phenom

    AMD's next architecture, K10, was a rather ambitious design. It is closely related to the K8, but it had several enhancements to the core and associated cache and memory controller. IPC was improved compared to K8, but K10's greatest advantage was its quad-core design that enabled it to run laps around the K8 dual-core CPUs in heavily-threaded applications.
    Unfortunately, the K10 ran into problems early on. The first K10 processors were based on the Barcelona configuration and sold as Opteron server processors. But a flaw in Barcelona (known as the TLB bug) could cause the CPU to lock up. AMD was able to release a software patch to keep the TLB bug at bay. However, it imposed a sizable performance hit. Owing to the power requirements to run multiple CPU cores simultaneously, the K10 Phenom processors also struggled to run at higher clock speeds. The fastest quad-core model was limited to 2.6 GHz, whereas dual-core K10 processors sold under the Athlon brand name manged to reach just 2.8 GHz.
    It should be noted that all first-generation K10 processors used the Agena die with part of the core disabled. Toliman, the triple-core variant, is actually the Agena die with one core disabled. The dual-core die was codenamed "Kuma," which is an Agena die with two cores disabled. Barcelona is identical to the Agena die as well, except that AMD fixed the TLB bug on Agena before releasing them to retailers. They were sold under the "Phenom," "Opteron" and "Athlon" product lines.
    AMD Phenom

    Code Name Agena Toliman
    Date November 2007 March 2008
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache (Per Core) 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache (Per Core) 512 KB (Full Speed) 512 KB (Full Speed)
    L3 Cache (Shared) 2 MB (@HyperTransport Frequency) 2 MB (@HyperTransport Frequency)
    Clock Speed 1.8 - 2.6 GHz 1.9 - 2.5 GHz
    Memory Controller Dual-Channel DDR2-1066 Dual-Channel DDR2-1066
    HyperTransport 2000 MHz 2000 MHz
    Core Count 4 3
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Fab 65 nm 65 nm
    Transistor Count 450 Million 450 Million
    Power Consumption 65 - 140 W (TDP) 65 - 95 W (TDP)
    Voltage 1.25 - 1.3 V 1.25 V
    Die Area 285 mm? 285 mm?
    Socket Socket AM2/AM2+ Socket AM2+



    AMD K10: Phenom II

    AMD managed to overcome the Phenom's shortcomings in the Phenom II. By transitioning to a 45nm process, power consumption dropped considerably, as did the amount of heat generated by the CPU, which enabled AMD to increase clock speed. Quad-core Phenom II processors based on the first Phenom II core, Deneb, managed to hit clock rates as high as 3.7 GHz. Because the die was significantly smaller than Agena, AMD was also able to triple the L3 cache size. Finally, Deneb transitioned to a DDR3 memory controller, but maintained backward compatibility with DDR2.
    AMD Phenom II X4

    Code Name Deneb
    Date January 2009
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Core) 64 KB + 64 KB
    L2 Cache (Per Core) 512 KB (Full Speed)
    L3 Cache (Shared 6 MB (@HyperTransport Frequency)
    Clock Speed 2.6 - 3.7 GHz
    Memory Controller Dual-Channel DDR2-1066, Dual-Channel DDR3-1333
    HyperTransport 2000 MHz
    Core Count 4
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Fab 45 nm
    Transistor Count 758 Million
    Power Consumption 65 - 140 W (TDP)
    Voltage 1.4 V
    Die Area 243 mm?
    Socket Socket AM2+/AM3



    AMD K10: Phenom II X2 and X3

    Similar to the first-generation Phenom processors, AMD recycled its semi-defective quad-core CPU die as triple- and dual-core dies. These processors kept the full 6 MB of L3 cache, but they typically ran at lower clock speeds. They were popular among enthusiasts, since it was sometimes possible to reactivate the disabled cores.
    AMD Phenom II X2 and X3

    Code Name Heka Callisto
    Date February 2009 June 2009
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache (Per Core) 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache (Per Core) 512 KB (Full Speed) 512 KB (Full Speed)
    L3 Cache (Shared) 6 MB (@HyperTransport Frequency) 6 MB (@HyperTransport Frequency)
    Clock Speed 2.4 - 3.2 GHz 2.8 - 3.5 GHz
    Memory Controller Dual-Channel DDR2-1066, Dual-Channel DDR3-1333 Dual-Channel DDR2-1066, Dual-Channel DDR3-1333
    HyperTransport 2000 MHz 2000 MHz
    Core Count 3 2
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Fab 45 nm 45 nm
    Transistor Count 758 Million 758 Million
    Power Consumption 65 - 95 W TDP 80 W TDP
    Voltage 1.4 V 1.4 V
    Die Area 243 mm? 243 mm?
    Socket Socket AM2+/AM3 Socket AM2+/AM3



    AMD K10: Athlon II

    AMD also released a series of low-end K10 processors branded Athlon II. To keep production costs low, these processors used CPU dies without L3 cache. The quad-core die was code-named Propus, and the dual-core was called Regor. A triple-core model called Rana used defective Propus dies with a single core disabled.
    AMD also used Deneb cores, but with the L3 cache disabled. This hurt performance, but with several CPU cores and clock speeds around 3 GHz, they still offered a reasonable experience.
    Because L3 cache increased power consumption of the CPU as a whole, AMD also sold several Propus and Regor dies as mobile Phenom II and Athlon II processors.
    AMD Athlon II

    Code Name Propus Regor
    Date September 2009 June 2009
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache (Per Core) 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache (Per Core) 512 KB (Full Speed) 1 MB (Full Speed)
    L3 Cache (Shared) None None
    Clock Speed 2.2 - 3.2 GHz 2.8 - 3.6 GHz
    Memory Controller Dual-Channel DDR2-1066, Dual-Channel DDR3-1333 Dual-Channel DDR2-1066, Dual-Channel DDR3-1333
    HyperTransport 2000 MHz 2000 MHz
    Core Count 4 2
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Fab 45 nm 45 nm
    Transistor Count N/A 234 Million
    Power Consumption 45 - 95 W TDP 25 - 65 W TDP
    Voltage 1.4 V 1.4 V
    Die Area N/A 117 mm?
    Socket Socket AM2+/AM3 Socket AM2+/AM3



    AMD K10: Sempron

    AMD extended its Sempron line again to serve as the absolute lowest-performance product in the K10 line. The K10 Semprons used the single-core Sargas die, which was harvested from defective Regor cores. The second core could sometimes be activated on these CPUs.

    AMD Phenom II X2 and X3

    Code Name Sargas
    Date July 2009
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Core) 64 KB + 64 KB
    L2 Cache (Per Core) 1 MB (Full Speed)
    L3 Cache (Shared) None
    Clock Speed 1.8 - 2.9 GHz
    Memory Controller Dual-Channel DDR2-1066, Dual-Channel DDR3-1333
    HyperTransport 2000 MHz
    Core Count 1
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Fab 45 nm
    Transistor Count 234 Million
    Power Consumption 45 W TDP
    Voltage 1.3 V
    Die Area 117 mm?
    Socket Socket AM2+/AM3
    AMD Athlon II X2, Sempron

    Nom de code Regor Sargas
    Date de sortie Juin 2009 Juillet 2009
    Architecture 64 bits 64 bits
    Bus de donn?e 64 bits 64 bits
    Bus d?adresse 64 bits 64 bits
    M?moire maximale 1 To 1 To
    Cache L1 (par core) 64 ko + 64 ko 64 ko + 64 ko
    Cache L2 (par core) 1 ou 2 Mo (fr?quence CPU) 512 ko ou 1 Mo (fr?quence CPU)
    Cache L3 (partag?) - -
    Fr?quence 1,6 - 3,6 GHz 1,8 - 2,9 GHz
    Contr?leur m?moire DDR2-1066, 2 canaux ou DDR3-1333, 2 canaux DDR2-1066, 2 canaux ou DDR3-1333, 2 canaux
    HyperTransport 1600, 1800, 2000 MHz 1800, 2000 MHz
    Nombre de cores 2 1
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Finesse de gravure 45 nm 45 nm
    Nombre de transistors 234 millions 234 millions
    Consommation 25 - 65 W (TDP) 45 W
    Tension 1,4 V 1,3 V
    Surface 117 mm? 117 mm?
    Connecteur Socket AM2+/AM3 Socket AM2+/AM3



    AMD K10: Phenom II X6

    In 2010, AMD stepped up its K10 product offerings again by introducing the Thuban and Zosma CPU dies. Thuban had a total of six CPU cores, and AMD used it in processors clocked as high as 3.3 GHz. AMD also introduced its Turbo Core technology with Thuban, which allowed the CPU to push its clock rate up to 3.7 GHz depending on the workload. This enabled Thuban to surpass Deneb in multitasking performance while also matching it in single-threaded performance.
    Zosma dies were harvested from partially defective Thuban cores, making them similar to Deneb, but with Turbo Core technology. Thanks to a matured 45nm process, Zosma and Thuban were also more energy efficient than Deneb.
    AMD Phenom II X6 and Zosma Phenom II X4

    Code Name Thuban Zosma
    Date 2010 2010
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache (Per Core) 64 KB + 64 KB 64 KB + 64 KB
    L2 Cache (Per Core) 512 KB (Full Speed) 512 KB (Full Speed)
    L3 Cache (Shared) 6 MB (@HyperTransport Frequency) 6 MB (@HyperTransport Frequency)
    Clock Speed 2.6 - 3.3 GHz / 3.3 - 3.7 GHz Turbo Core 2.7 - 3.5 GHz
    Memory Controller Dual-Channel DDR2-1066, Dual-Channel DDR3-1333 Dual-Channel DDR2-1066, Dual-Channel DDR3-1333
    HyperTransport 2000 MHz 2000 MHz
    Core Count 6 4
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Fab 45 nm 45 nm
    Transistor Count 904 Million 904 Million
    Power Consumption 95 - 125 W TDP 95 -125 W TDP
    Voltage 1.4 V 1.4 V
    Die Area 346 mm? 346 mm?
    Socket Socket AM3 Socket AM3



    AMD K10: Fusion/Llano

    AMD's Fusion project came to fruition in July 2011, when the company released its first APUs, code-named "Llano." The design combined a large number of AMD's Radeon Stream Processors based on the TeraScale 2 architecture with the company's K10 CPU cores. The underlying concept was similar to AMD's Geode line, which hadn't been updated in years. But where the Geode was designed as a low-power/performance solution, Llano was meant to be a higher-performance product.
    It was never meant to compete in the high-end, but the idea was to create a SKU that could give reasonable CPU and graphics performance all in one. Llano suffered from a lack of L3 cache, and the iGPU was far too slow to keep most gamers happy, but for casual gamers that didn't mind lower graphics settings, it performed well enough.
    AMD Llano

    Code Name Llano
    Date July 2011
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Core) 64 KB + 64 KB
    L2 Cache (Per Core) 1 MB (Full Speed)
    L3 Cache (Shared) None
    Clock Speed 2.1 - 3 GHz
    Memory Controller Dual-Channel DDR3-1866
    Core Count 2, 3, 4
    SIMD MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a
    Fab 32 nm
    Transistor Count 1,178 Million
    Power Consumption 65 - 100 W
    Voltage 0.45 - 1.4125 V
    Die Area 227 mm?
    Socket Socket FM1
    iGPU TeraScale 2 (Radeon HD 5000, rebranded as Radeon HD 6000)



    AMD Bobcat

    To be more competitive with Intel's Atom and ARM's low-power microprocessors, AMD introduced its Bobcat architecture in 2011. Since Bobcat was designed to be efficient, it ran at fairly low clock speeds; the highest-performing model reached 1.75 GHz. Bobcat is technically an APU, and it contains an iGPU with 80 Stream Processors based on the TeraScale 2 architecture. The iGPU is clocked rather conservatively as well in order to keep power consumption low.
    AMD Bobcat

    Code Name Desna, Ontario, Zacate
    Date 2011
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Core) 32 KB + 32 KB
    L2 Cache (Per Core) 512 KB (Full Speed)
    L3 Cache (Shared) None
    Clock Speed 0.8 - 1.75 GHz
    Memory Controller Single-Channel DDR3L-1333
    Core Count 1 - 2
    SIMD MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX
    Fab 40 nm
    Transistor Count N/A
    Power Consumption 4.5 - 18 W TDP
    Voltage 0.5 - 1.4 V
    Die Area 107 mm?
    Socket AM1
    iGPU Architecture TeraScale 2
    iGPU Shader Count 80


    AMD Bulldozer: Zambezi

    In October 2011, AMD introduced the successor to its K10 architecture, code-named "Bulldozer." With Bulldozer, AMD attempted to use high core count and clock speed to outperform Intel's recently-released Sandy Bridge. The cost of this clock rate-focused design, however, was a marked drop in IPC compared to the K10 architecture, and the design has been plagued with problems. The first Bulldozer chip, code-named Zambezi, was not able to cleanly out-perform Thuban Phenom II X6 CPUs, let alone beat Sandy Bridge. Part of the problem came from the use of a Multi-Core Module (MCM) that contains two integer cores and one FPU. As the two integer execution units have to share the FPU, this can lead to stalls in the pipeline.

    The design has also been criticized for being power-hungry and running too hot, though that stems from direct comparisons between Bulldozer and Sandy Bridge.

    AMD Bulldozer Zambezi

    Code Name Zambezi
    Date October 2011
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Module) 64 KB + (2 x 16 KB)
    L2 Cache (Per Module) 2 MB (Full Speed)
    L3 Cache (Shared) 8 MB
    Clock Speed 2.8 - 4.2 GHz (4.3 GHz Turbo)
    Memory Controller Dual-Channel DDR3-1866
    HyperTransport 2600 MHz
    Core Count 4, 6, 8
    SIMD MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX
    Instructions AES, FMA4, XOP
    Fab 32 nm
    Transistor Count N/A
    Power Consumption 95 - 125 W
    Voltage 0.95 - 1.4125 V
    Die Area 316 mm?
    Socket AM3+




    AMD Piledriver: Trinity And Richland

    A year after Bulldozer debuted, AMD released a revised architecture known as Piledriver. Piledriver was initially released with Trinity, the company's second-gen APU. It saw clock speed increase by about 10 percent, and that, in conjunction with architectural enhancements, pushed performance up by roughly 15 percent without increasing power consumption.
    On the iGPU side, Trinity moved to the TeraScale 3 architecture used inside of AMD's Radeon HD 6900-series GPUs. This helped to increase graphics performance over Llano.
    Richland, in turn, was a slightly improved Piledriver part. It performed just slightly better than Trinity due to higher clock speeds. It also managed to reduce power consumption and heat somewhat. The performance gap between mobile Trinity APUs and mobile Richland APUs was greater than on the desktop, owing to the improved thermals and power consumption.
    AMD Trinity And Richland APUs

    Code Name Trinity Richland
    Date October 2012 May 2013
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache (Per Module) 64 KB + (2 x 16 KB) 64 KB + (2 x 16 KB)
    L2 Cache (Per Module) 2 MB (Full Speed) 2 MB (Full Speed)
    L3 Cache (Shared) - -
    Clock Speed 2.9 - 3.8 GHz (4.2 GHz Turbo) 2.1 - 4.1 GHz (4.4 GHz Turbo)
    Memory Controller Dual-Channel DDR3-1866 Dual-Channel DDR3-2133
    Core Count 2 - 4 2 - 4
    SIMD MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX
    Instructions AES, BMI1, F16C, FMA3, FMA4, TBM, XOP AES, BMI1, F16C, FMA3, FMA4, TBM, XOP
    Fab 32 nm 32 nm
    Transistor Count 1,303 Million 1,300 Million
    Power Consumption 65 - 100 W 45 - 100 W
    Voltage 0.825 - 1.475 V N/A
    Die Area 246 mm? 246 mm?
    Socket FM2 FM2
    iGPU TeraScale 3 (Radeon HD 6900) TeraScale 3 (Radeon HD 6900 - Rebranded As Radeon HD 8000)



    AMD Piledriver: Vishera

    AMD also applied its Piledriver architecture to the FX family, displacing Zambezi in favor of Vishera.
    AMD Bulldozer Vishera

    Code Name Vishera
    Date October 2012
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Module) 64 KB + (2 x 16 KB)
    L2 Cache (Per Module) 2 MB (Full Speed)
    L3 Cache (Shared) 8 MB
    Clock Speed 3.3 - 4.7 GHz (5 GHz Turbo)
    Memory Controller Dual-Channel DDR3-1866
    HyperTransport 2600 MHz
    Core Count 4, 6, 8
    SIMD MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX
    Instructions AES, BMI1, F16C, FMA3, FMA4, TBM, XOP
    Fab 32 nm
    Transistor Count N/A
    Power Consumption 95 - 125 W (220 W)
    Voltage 0.875 - 1.425 V
    Die Area N/A
    Socket AM3+

  3. #3
    OverclockZone Member 111111's Avatar
    Join Date
    14 Nov 2007
    Location
    Hiroshima, Japan.

    Default



    AMD Steamroller: A GCN APU

    In 2014, AMD updated its APU line again with the new Steamroller architecture. AMD shifted to a new 28nm process that favored chip density over clock speeds in order to be more compatible with its graphics technology. The CPU demonstrated a reasonable increase in IPC over its predecessor, thanks in part to a larger L1 cache and additional internal registers. It wasn't able to hit the same clock speeds as Richland though, so overall performance didn't increase much.
    The graphics side of the APU improved drastically, however, owing to the new transistor technology, an increase in shader count, and a move to AMD's GCN GPU architecture. The APU featured a number of other enhancements, such as being the first HSA-compatible APU, the addition of AMD's TrueAudio DSP technology and support for PCIe 3.0.
    The first Steamroller APUs use a configuration known as Kaveri. The APU line was later refreshed with Godavari, which benefits mostly from higher clock speeds.

    Code Name Kaveri Godavari
    Date January 2014 May 2015
    Architecture 64-bit 64-bit
    Data Bus 64-bit 64-bit
    Address Bus 64-bit 64-bit
    Maximum Memory Support 1 TB 1 TB
    L1 Cache (Per Module) 96 KB + (2 x 16 KB) 96 KB + (2 x 16 KB)
    L2 Cache (Per Module) 2 MB (Full Speed) 2 MB (Full Speed)
    L3 Cache (Per Module) None None
    Clock Speed 3.1 - 3.7 GHz (Turbo 4 GHz) 2.9 - 3.9 GHz (Turbo 4.1 GHz)
    Memory Controller Dual-Channel DDR3-2133 Dual-Channel DDR3-2133
    Core Count 2 - 4 2 - 4
    SIMD MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX
    Instructions AES, BMI1, F16C, FMA3, FMA4, TBM, XOP AES, BMI1, F16C, FMA3, FMA4, TBM, XOP
    Fab 28 nm 28 nm
    Transistor Count 2.41 Billion N/A
    Power Consumption 65 - 95 W 65 - 95 W
    Voltage N/A N/A
    Die Area 245 mm? N/A
    Socket FM2+ FM2+
    iGPU GCN Radeon R5/R7 GCN Radeon R5/R7



    AMD Jaguar

    AMD introduced its Jaguar architecture in 2014 to replace the aging Bobcat core. Jaguar increased the CPU core count to four and moved to a faster GCN-based graphics processor with 128 shaders. IPC shot up by roughly 15 percent as well, alongside a boost in clock speed. Overall, Jaguar is significantly faster than Bobcat in every way.
    The Jaguar architecture in also used inside of the Xbox One and Playstation 4. The models inside of these game consoles have significantly higher core counts on both the CPU and iGPU, however, and Jaguar-based products available in other devices are considerably slower.
    AMD Jaguar

    Code Name Kabin, Temash
    Date April 2014
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Core) 32 KB + 32 KB
    L2 Cache (Per Core) 512 KB (Full Speed)
    L3 Cache (Shared) None
    Clock Speed 1.3 - 2.05 GHz
    Memory Controller Dual-Channel DDR3-1600
    Core Count 2 - 4
    SIMD MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX
    Fab 28 nm
    Transistor Count N/A
    Power Consumption 3.9 - 25 W TDP
    Voltage 0.5 - 1.4 V
    Die Area 107 mm?
    Socket AM1
    iGPU Architecture GCN Radeon R3
    iGPU Shader Count 128



    Excavator: The End Of Bulldozer

    The last architecture that AMD plans to produce based on Bulldozer is known as Excavator, which is used inside of AMD Carrizo-based APUs. Relatively few of these products have been released thus far, so we can't be sure what the clock speed limit will be on these parts. Carrizo is designed to have significantly higher transistor density (than prior Bulldozer-based processors), which helps to reduce the die area and lower power consumption. AMD reworked the cache inside of Excavator, too.
    The processor has less L2 cache, but twice as much L1 cache when compared to Steamroller. Because the L1 cache is several times faster than the L2 cache, this helps to boost IPC performance. The branch prediction target buffer was increased by 50 percent as well, to 768 KB, which further helps to improve performance. The graphics processor also gained 512 KB of dedicated L2 cache to increase graphics processing power. Rearranging the cache on the APU also helped to lower the power consumption, as cache tends to be fairly power hungry, and this new configuration has less overall cache on die.



    AMD Excavator

    Code Name Carrizo
    Date 2015
    Architecture 64-bit
    Data Bus 64-bit
    Address Bus 64-bit
    Maximum Memory Support 1 TB
    L1 Cache (Per Module) 192 KB + (2 x 32 KB)
    L2 Cache (Per Module) 1 MB (Full Speed)
    L3 Cache (Shared) None
    Clock Speed 3.5 GHz (Athlon X4 845, Carrizo clock speed range unknown)
    Memory Controller Dual-Channel DDR3
    Core Count 2 - 4
    SIMD MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1/4.2, AVX
    Fab 28 nm
    Transistor Count N/A
    Power Consumption 65 W TDP (Athlon X4 845, Carrizo power consumption range unknown)
    Voltage N/A
    Die Area N/A
    Socket FM2+
    iGPU Architecture GCN Radeon R3
    iGPU Shader Count 512

    CREDIT : http://www.tomshardware.com/

    Version แปลไทยทั้งหมดกำลังจัดทำครับ ติดตามได้ที่กระทู้:ROZ - Republic Of Zen : Society for AMD Citizens


  4. #4
    OverclockZone Member Hirasawa's Avatar
    Join Date
    8 May 2011

    Default


  5. #5
    OverclockZone Member micronz's Avatar
    Join Date
    27 Aug 2010

    Default

    ขยันมากตา อั๋นซัง ค่อยมาเสริมให้เป็นช่วงๆๆๆ ปั่นแบบ ต่อ

  6. #6
    OverclockZone Member 111111's Avatar
    Join Date
    14 Nov 2007
    Location
    Hiroshima, Japan.

    Default

    ต้องช่วยไอ่คิตตี้มันครับลุง เดี๋ยวมันจะหนี

  7. #7
    OverclockZone Member MooNoiOCZ's Avatar
    Join Date
    6 Apr 2014

    Default

    เคยใช้80286 แต่ไม่รู้ใช่ชิพ AMD มั้ย
    ที่แน่ๆคือย้ายจากPentium120 มาเป็นK6-II เพราะ3DNow ล้วนๆเลย แล้วก็ต่อด้วยK6-III จนมาถึงATHLON 64.....และRYZEN (ยังไม่ได้ซื้อ)

  8. #8
    OverclockZone Member kitti3's Avatar
    Join Date
    9 Dec 2009
    Location
    ณ ห้วงแห่งจริง

    Default

    ช่วยตูยังไง

    Send form My Asus ZenFone 3 Laser using Tapatalk

  9. #9
    OverclockZone Member kitti3's Avatar
    Join Date
    9 Dec 2009
    Location
    ณ ห้วงแห่งจริง

    Default

    ตั้งมู้มาใหม่มันไม่เกี่ยวเลยป่าวฟะ

    Send form My Asus ZenFone 3 Laser using Tapatalk

  10. #10
    OverclockZone Member 111111's Avatar
    Join Date
    14 Nov 2007
    Location
    Hiroshima, Japan.

    Default

    เดี๋ยวค่อยเอาไปยัดเข้าไง version แปลไทยแล้ว รอไปก่อน อ่านไม่หมดนี่หว่า หาเรื่องเจ็บตัวอีกละ

  11. #11
    OverclockZone Member redondo16's Avatar
    Join Date
    17 Apr 2007

    Default

    ที่เคยใช้ AthlonXP 2000+ > Semporn LE1100 -> Athlon64 X2 4800+ -> AthlonX4 845

    ใน laptop Turion 64 MK36 ตอนนี้สั่ง Athlon X2 TK42 มากะลองวิชาเปลี่ยน CPU

  12. #12
    OverclockZone Member 111111's Avatar
    Join Date
    14 Nov 2007
    Location
    Hiroshima, Japan.

    Default

    โอ้ว วิชาเปลี่ยน เส้นเอ็น เอ้ย เปลี่ยน CPU

  13. #13
    OverclockZone Member dekmepz's Avatar
    Join Date
    28 Oct 2012

    Default

    บ่งบอกถึงอายุ คนตั้ง จขกท. เลยเน้อ

  14. #14

    Default

    Quote Originally Posted by dekmepz View Post
    บ่งบอกถึงอายุ คนตั้ง จขกท. เลยเน้อ
    ...................................

    อ่ะ ให้เด็กเมฟ

    IMG00435-20110728-1430-5.jpg

  15. #15
    OverclockZone Member dekmepz's Avatar
    Join Date
    28 Oct 2012

    Default


  16. #16
    OverclockZone Member 111111's Avatar
    Join Date
    14 Nov 2007
    Location
    Hiroshima, Japan.

    Default



    แล้วเจ้าเดกเมฟ ใช้อะไรของ AMD มามั่ง อย่าบอกนะว่าไม่เคย จะเนรเทศให้

  17. #17
    OverclockZone Member nonpatan's Avatar
    Join Date
    21 Apr 2014

    Default

    ผมใช้ cpu ตัวแรกสมัยเรียน มหาลัย ก็คือ Duron นี่แหละ--->สมัยเริ่มทำงานใหม่ๆ Athlon ---------------------------> ยาวๆมาเลยยังไม่มี pc ใช้ ตอนนี้รอ ryzen (ระหว่างรอ ryzen ใช้ notebook intel)

  18. #18
    OverclockZone Member nonpatan's Avatar
    Join Date
    21 Apr 2014

    Default

    Quote Originally Posted by nonpatan View Post
    ผมใช้ cpu ตัวแรกสมัยเรียน มหาลัย ก็คือ Duron นี่แหละ--->สมัยเริ่มทำงานใหม่ๆ Athlon ---------------------------> ยาวๆมาเลยยังไม่มี pc ใช้ ตอนนี้รอ ryzen (ระหว่างรอ ryzen ใช้ notebook intel)
    จำได้ว่าสมัยเรียนมหาลัยนี่แหละ amd ดังมากเลย แรงกว่า intel อีก มาตกม้าตายกับ FX เชียร์ไม่ขึ้นเลย

  19. #19
    OverclockZone Member dekmepz's Avatar
    Join Date
    28 Oct 2012

    Default

    Quote Originally Posted by 111111 View Post


    แล้วเจ้าเดกเมฟ ใช้อะไรของ AMD มามั่ง อย่าบอกนะว่าไม่เคย จะเนรเทศให้
    Pentium 4 , Core 2 duo ไงทำไมเรอะ


  20. #20
    OverclockZone Member O_ho's Avatar
    Join Date
    1 Jun 2010

    Default

    เมื่อลุง FX กับหลาน Ryzen วิ่งไปด้วยกัน


Page 1 of 2 12 LastLast

Bookmarks

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •